Computer systems employ a variety of memory, including magnetic disk and semiconductor memory systems. Typically, magnetic disk storage systems target large memory, low speed applications; whereas, semiconductor storage systems target high-speed, low capacity applications. However, with semiconductor devices becoming less expensive and offering greater capacities, the computer industry has begun using solid-state disk storage systems to provide large, “disk-like” storage capacity with fast, “solid-state-like” speed of performance.
Known, exemplary solid-state disk drives comprise a plurality of DRAM or FLASH memory chips. In general, the DRAM chips are used for storing data temporarily, and the FLASH chips used for more permanent data retention. To improve their data storage reliability, the solid-state disk drives may incorporate error correction logic for overcoming possible soft-error limitations, or perhaps a failed device from amongst the plurality of chips that may make-up the solid-state disk drive.
Error correction coding (ECC) circuits may encode data for storage and decode the data when read therefrom. Known ECC circuits, for example Reed-Solomon, may work with a codeblock, or codeword, that comprises a plurality of symbols (data bit groups). When employed with a solid-state disk that comprises a plurality of discrete memory chips, the ECC circuits may employ interleaved symbol techniques for distribution of the data of the ECC codeblock across the plurality of memory chips of the solid-state disk. Additionally, the error correction code (ECC) may provide a sufficient length error correction capability, such that a failure of one or more memory chips from amongst the plurality of chips may be accommodated with correction by the ECC without exhausting its correction length.
DRAM or FLASH devices are exemplary forms of memory of known solid-state disks. Such memory chips exchange their data in small bytes—i.e., using word oriented data transfers. Therefore, ECC circuits and methods of known, exemplary solid-state disks may include symbol-to-word, interleave converters that convert the ECC codeblock symbols into pre-formatted words that may be written into and across the separate memory chips of the solid-state disk. Likewise, when reading data, conversion circuits may receive data words from the plurality of memory chips, convert the received words into symbols of an ECC codeblock for processing by ECC circuitry.
DRAM memory is a volatile form of memory. When in use, the device periodically refreshes its memory contents internally to assure data retention. However, being a volatile device, the DRAM loses data with loss of power. Accordingly, such DRAM's are known for temporary data storage applications, wherein new information is typically obtained and provided over the course of its operation.
On the other hand, non-volatile memories, e.g., FLASH or EEPROM, are known to provide long-term data retention. Once they have been programmed with data, the non-volatile devices may be expected to retain their data with high reliability and low error rate.
As the geometries of DRAM and FLASH devices decrease, their probability of experiencing a random or soft-error during a read operation may increase, which in-turn may add additional demands to the error correction methods. Recently, some memory manufactures have been directing their attention to alternative non-volatile memories, such as magneto-resistive, ferro-magnetic, and ferroelectric memory devices. Such alternatives may offer enhanced memory capacities with densities not previously practical in planar DRAM and FLASH technologies. For example, some ferroelectric designs may stack arrays of ferroelectric memory cells. However, for some of these memories, for example, ferroelectric, the memory may fatigue over an extended use and time. Additionally, the ferroelectric memories may employ a destructive read procedure wherein the state of a memory cell is cleared by its read process. Further, the ferroelectric memories may enable enhanced capacities with provision of stacking of the layers of cells in 3-D fashion, which capacities have not been practical in planar DRAM and FLASH technologies. Memory technologies and densities have evolved to the point that an individual memory chip may contain the equivalent of multiple previous generation memory chips. This may include repetitive implementations of the address decoders, memory blocks, multiplexers and sense amplifiers. The evolution of memory cell density, addressing schemes and the introduction of new memory storage materials requires the revisiting of the architecture of fundamental memory building blocks, the integrated circuit. Such architectural partitioning considerations may influence the redundancy circuits and allow isolation of high risk areas for the components and circuits that may be associated with memory arrays.